For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete, matches the program order of the instructions, providing it does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, software must insert a memory barrier instruction between the memory access instructions, see Software ordering of memory accesses.
However, the memory system does guarantee some ordering of accesses to Device and Strongly-Ordered Memory. For two memory access instructions A1 and A2, in case of those are initiated by the same master interface, and if A1 occurs before A2 in program order, the ordering of the memory accesses caused by two instructions is:
The use of DMB is rarely needed in Cortex-M processors because they do not reorder memory transactions. However, it is needed if the software is to be reused on other ARM processors, especially multi-master systems. For example:
DMA controller configuration. A barrier is required between a CPU memory access and a DMA operation.
关于ARM，上面这个资料好像是说取决于目标架构，Cortex M0 到 M4F等不需要屏障。
但是像是Cortex-M7这样的就需要。我一开始也是在看这个文档才想起来去了解内存顺序相关知识。
目前一个比较尴尬的地方在于RISC-V的《 The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture》中【 RVWMO Memory Consistency Model, Version 2.0】章节里的信息：
This chapter defines the memory model for regular main memory operations. The interaction of the memory model with I/O memory, instruction fetches, FENCE.I, page table walks, and SFENCE.VMA is not (yet) formalized. Some or all of the above may be formalized in a future revision of this specification. Future ISA extensions such as the V vector and J JIT extensions will need to be incorporated into a future revision as well.
好像是说主内存和I/O内存的交互暂未正式化，需要等未来版本
然后RISC-V的 Unprivileged ISA附录A【 Appendix A: RVWMO Explanatory Material, Version 0.1】中有一些I/O相关的描述，目前还在看。
For I/O, the load value axiom and atomicity axiom in general do not apply, as both reads and writes might have device-specific side effects and may return values other than the value “written” by the most recent store to the same address. Nevertheless, the following preserved program order rules still generally apply for accesses to I/O memory: memory access a precedes memory access b in global memory order if a precedes b in program order and one or more of the following holds:
a precedes b in preserved program order as defined in [memorymodel], with the exception that acquire and release ordering annotations apply only from one memory operation to another memory operation and from one I/O operation to another I/O operation, but not from a memory operation to an I/O nor vice versa
a and b are accesses to overlapping addresses in an I/O region
a and b are accesses to the same strongly ordered I/O region
a and b are accesses to I/O regions, and the channel associated with the I/O region accessed by either a or b is channel 1
a and b are accesses to I/O regions associated with the same channel (except for channel 0)
