Last updated: Jan/15/2026 @https://github.com/sophgo/linux/wiki
CV18XX
- N/A
SG2042
- RTC: v1 submitted and applied on sophgo/dt/riscv, will picked by 6.20. Thank you, Michael Orlitzky.
- PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports: v1 submitted.
- riscv: dts: Move plic/clint into sg2042-cpu and sort peripherals by addresses: v1 submitted.
SG2044
- PCI/sophgo: Avoid L0s and L1 on Sophgo 2044 PCIe Root Ports: Applied on pci/controller/dwc-sophgo. Will be picked by 6.20.
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2026 新年第一帖!
Yours,
Chen